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Advances in Testing: New Techniques For Reducing Cost of Test
Event Length: Approximately 40 minutes

This seminar will show how to increase test throughput for devices on the wafer and packaged level as well as techniques for integrating high-speed test procedures by taking advantages of advances in current instrumentation design, particularly the addition of on-board test sequencing.

In this seminar, you will learn and understand::
  • Typical instrumentation optimization (hardware and software) for wafer and packaged level devices.
  • Ideal code organization for increased throughput.
  • Hints and tips for improving test throughput without decreasing accuracy.
This seminar is recommended for Engineers, researchers, and scientists in areas such as traditional and compound Semiconductor, materials science, and Electrical Component Production (LED, Resistors, etc..) who wish to get a better understanding of electrical measurements.

Jason Chonko, Senior Applications Engineer for Keithley Instruments, presents the seminar.


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